Presentation description

This project addresses the growing need for fast and energy-efficient machine learning (ML) inference on edge devices by developing a hybrid System-on-Chip (SoC) architecture. The proposed design enhances a RISC-V processor with embedded FPGA (eFPGA) fabrics and Custom Compute Units (CCUs), combining the performance of ASICs with the flexibility of FPGAs. This hybrid approach enables the acceleration of TensorFlow Lite models while maintaining adaptability for evolving ML workloads.
Unlike existing solutions that rely solely on either ASIC or FPGA implementations, this project proposes a dual-core design. It uses a hard RISC-V core for general-purpose processing and an eFPGA-based CCU to accelerate ML operations tailored to specific models. This allows selective offloading of compute-intensive tasks, such as SIMD multiply-accumulate operations, to custom hardware logic.
The Ibex core, a 32-bit open-source RISC-V processor, is modified to support custom instructions that trigger specific operations implemented in the eFPGA fabric. This setup allows certain performance-critical tasks to run more efficiently in hardware, improving speed and reducing CPU load. To take advantage of this, we adapt parts of TensorFlow Lite models to better fit the hardware, including restructuring key functions like multiply-accumulate to run on the custom compute unit (CCU). This approach not only improves performance for targeted workloads but also contributes to the open-source hardware community by adding reusable components and system templates through the ESP framework.